1. Field of the Invention
This invention relates to an A/D converter circuit for converting an inputted analog voltage into a digital value.
The present invention further relates to supply of bias current to such a function circuit as an AD converter circuit and more particularly to supply of bias current to the AD converter circuit having a parallel-type A/D converter section.
2. Description of Related Art
Parallel A/D converter circuits (hereinafter also called A/D-converters) which have numerous resistor devices arrayed in series to divide a standard voltage and use numerous comparators to compare, by clock signal cycles, reference voltages of the connection points with an inputted analog voltage in parallel and generate a digital value on the basis of the outputs of the comparators are known. In this kind of parallel-type A/D-converter, for example for 8-bit A/D-conversion (also simply called conversion), 255(=28−1) comparators are used.
However, the amplitude of the inputted analog voltage does not at all times have the maximum amplitude (maximum input width) that can be converted with the A/D-converter. And also the frequency of the inputted analog voltage is not at all times a high frequency such as for example ½ of the frequency of the clock signal. Generally, the amplitude of the analog voltage is smaller than the maximum amplitude that can be A/D-converted, and a frequency amply low compared to the clock signal is also normal.
In this case, with respect to the inputted analog voltage at a point in time given by a certain clock signal, there is a limit to the change amount of the analog voltage by which it can change by the time given by the next clock signal. That is, if the analog voltage inputted at a point in time determined by a certain clock signal is known, from this it is possible with a certain width to predict the analog voltage that will be inputted at the point in time determined by the next clock signal.
On the other hand, although in a normal A/D-converter all of the comparators are operated together by the clock signal, if as described above the inputted analog voltage can be predicted, it is possible by operating only the necessary comparators and resting the rest of the comparators to make this A/D-converter low in consumed power without the resolution or conversion result (digital value) of the A/D-converter changing.
In Patent Document 1 (Japanese Laid-Open Patent Publication No. 2000-341124), the following kind of A/D converter circuit is set forth. That is, using two comparators of a former stage, the inputted analog voltage is classified as one of three levels, a low level, a high level and an intermediate level. And numerous comparators arrayed in parallel in a latter stage to that are divided into three groups, and groups of comparators to be operated are selected on the basis of first and second control signals from the two comparators of the former stage. Specifically, when the analog voltage is at the intermediate level, all the comparators of the three groups are operated. However, when the analog voltage is at the low level, only the comparators of the groups corresponding to the intermediate level and the low level are operated, and the comparators corresponding to the high level are not operated. And when the analog voltage is at the high level, only the comparators of the groups corresponding to the intermediate level and the high level are operated, and the comparators of the group corresponding to the low level are not operated. In this way, by not operating some of the comparators, the consumed power of the A/D-converter is reduced.
However, in the invention set forth in this Patent Document 1, the two comparators of the former stage are differential amplifier type comparators, which do not use a clock signal, and continuously compare and classify the analog voltage and select the groups of comparators to be operated Thus, the groups of comparators of the latter stage are selected on the basis of the analog voltage of immediately before conversion by the comparators of the latter stage (more exactly, depending on the characteristics of the comparators of the former stage, in the past by the amount of the time delay to when their output changes in correspondence with a change in the analog voltage inputted to them). That is, to select the comparators of the latter stage, the timing with which the comparators of the former stage fetch the analog value is determined by the characteristics of the comparators of the former stage. Furthermore, the time delay of the comparators of the former stage is different between when the change of the analog value inputted is large and when it is small (when the change in the input is large, it takes time for the corresponding change in output to finish). Consequently, if looked at from the comparators of the latter stage, the timing at which the selection of the comparators of the latter stage is decided changes due to changes in the analog value, and there are cases where the groups of comparators cannot be selected appropriately, so that different groups from those which should properly be selected are selected.
And, because when the analog voltage is at the intermediate level all the comparators of the three groups are operated and so on, the number of comparators which are not operated is small and there is a limit to the consumed power reduction effect.
As an example of the function circuit in prior art, FIG. 10 shows a circuit diagram of the parallel-type AD converter circuit. The high voltage level VRH and the low voltage level VRL are divided equally with eight divided resistors RF110–RF180 and supplied as the reference voltages V110–V170. Then, the input voltages VIN are compared therewith by seven comparators C110–C170 at the same time. As a comparison result, output signals OUT110–OUT170 obtained in a digital signal are divided to high level and low level with a predetermined output signal as a boundary and outputted depending on the voltage level of the input voltage VIN. By encoding the output signals OUT110–OUT170, a 3-bit digital signal is obtained.
The respective comparators C110–C170 are of the same circuit unit. Further, a predetermined bias current needs to be supplied for the respective comparators C110–C170 to execute the comparison operation. When the parallel-type A/D converter circuit executes A/D conversion operation, the predetermined bias current is supplied to all the comparators C110–C170. Current consumption occurs in each comparator.
However, the input voltage VIN is analog voltage and the voltage change quantity of the input voltage VIN in A/D conversion operation to be carried out at each predetermined timing is limited. That is, in the A/D conversion operation about the input voltage VIN, which is an analog voltage signal, a voltage value of the input voltage VIN has to be detected with only comparators existing within a voltage range which may change at adjacent conversion timings. Thus, in a comparator having a voltage value within a voltage range which may not be inputted at the adjacent conversion timing, as the reference voltage, unnecessary current consumption in comparator which is unnecessary for the A/D conversion operation occurs under a conventional technology in which the bias current is always supplied, which is a problem to be solved.
As regards other circuits than the AD converter circuit, a function circuit having plural circuit units and in which their circuit operations are carried out by supplying the bias current to each of them may have the same problem. That is, for example, although in a function circuit in which the operation condition of each circuit unit is switched over depending on bias current setting so as to determine a next operation condition depending on a current operation condition, only the circuit units which can be expected have to be supplied with the bias current, according to the conventional technology, the bias current is always supplied to all the circuit units so that unnecessary current consumption occurs, which is a problem to be solved.